A source synchronous data strobe serves to compensate for the delays in the transmit path of a device that is transmitting data and the receive path of a device receiving this data. The size of these delays are a function of the speed, and variation in path speed, of a semiconductor device over its operating conditions and manufacturing tolerances.
Typically the data strobe interconnect lines between devices are left in a tristate, or quiet state, when responsibility for generating a data strobe is transferred from one device to another. As a result of these quiet periods, the data strobe does not have a predetermined, constant frequency, but resembles a clock being briefly turned on and off. During periods that multiple cycles of the data strobe are generated by a single device, the data strobe signal suffers from standing wave phenomena. The first edge, and perhaps the first few edges of a data strobe will typically arrive in-phase with respect to the data. However, subsequent edges of the data strobe may shift due to reflections of previous data strobe edges, and therefore will not be in phase with respect to the data. In other words, the data strobe would begin to appear more like a free running clock.
As memory bus speeds have increased, the benefits of using source synchronous data strobes in memory systems have decreased. Over time it is apparent that data strobes will need to be modified to accommodate systems that run faster. Due to manufacturing costs and economies of scale, it would be beneficial if a new system design that addresses the problems with data strobes were compatible with products using source synchronous data strobes.